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Course Details
KTO KARATAY UNIVERSITY
Mühendislik ve Doğa Bilimleri Fakültesi
Programme of Mechatronics Engineering
Course Details
Course Code Course Name Year Period Semester T+A+L Credit ECTS
05581010 FPGA Based Design 4 Spring 8 3+1+0 5 5
Course Type Elective
Course Cycle Bachelor's (First Cycle) (TQF-HE: Level 6 / QF-EHEA: Level 1 / EQF-LLL: Level 6)
Course Language Turkish
Methods and Techniques Lecture, Problem Solving, Laboratory, Project
Mode of Delivery Face to Face
Prerequisites There is no prerequisite for the course.
Coordinator -
Instructor(s) -
Instructor Assistant(s) -
Course Content
PLA, PAL design, RTL introduction, HDL (VHDL/Verilog) coding principles, gate level coding, behavioural coding, FPGA programming applications
Objectives of the Course
Ability to code and implement for FPGA-based systems
Contribution of the Course to Field Teaching
Basic Vocational Courses
Specialization / Field Courses X
Support Courses
Transferable Skills Courses
Humanities, Communication and Management Skills Courses
Relationships between Course Learning Outcomes and Program Outcomes
Relationship Levels
Lowest Low Medium High Highest
1 2 3 4 5
# Program Learning Outcomes Level
P2 Ability to identify, formulate and solve complex Mechatronics Engineering problems; ability to select and apply appropriate analysis and modeling methods for this purpose. 5
P4 Ability to select and use modern techniques and tools necessary for the analysis and solution of complex problems encountered in Mechatronics Engineering applications; Ability to use information technologies effectively 5
P5 An ability to design and conduct experiments, collect data, analyze, and interpret results for the study of complex engineering problems or research topics specific to Mechatronics Engineering 5
P7 Ability to communicate effectively orally and in writing; knowledge of at least one foreign language; ability to write effective reports and understand written reports, to prepare design and production reports, to make effective presentations, to give and receive clear and understandable instructions 5
Course Learning Outcomes
Upon the successful completion of this course, students will be able to:
No Learning Outcomes Outcome Relationship Measurement Method **
O1 Ability to know the design of programmable logic arrays P.2.42 1
O2 Ability to make hardware description language application P.4.19 1,7
O3 Ability to code FPGA at gate level P.5.20 1,7
O4 Ability to code Behavioural FPGA P.5.21 1,7
O5 Ability to make FPGA application P.5.22 7
O6 Ability to prepare and present technical documents such as technical reports and presentations P.7.2 5
** Written Exam: 1, Oral Exam: 2, Homework: 3, Lab./Exam: 4, Seminar/Presentation: 5, Term Paper: 6, Application: 7
Weekly Detailed Course Contents
Week Topics
1 Historical perspective: PLA, PAL, CPLD, FPGA
2 Register transfer language
3 Register transfer language
4 Register transfer language
5 Hardware description language (VHDL, Verilog)
6 Hardware description language (VHDL, Verilog)
7 Hardware description language (VHDL, Verilog)
8 Gate level coding
9 Gate level coding
10 Behavioral coding
11 Behavioral coding
12 Applications of FPGA programming
13 Applications of FPGA programming
14 Applications of FPGA programming
Textbook or Material
Resources https://sites.google.com/site/abulentusakli/
Evaluation Method and Passing Criteria
In-Term Studies Quantity Percentage
Attendance 1 5 (%)
Laboratory 1 15 (%)
Practice - -
Course Specific Internship (If Any) - -
Homework - -
Presentation - -
Projects 1 20 (%)
Quiz - -
Midterms 1 30 (%)
Final Exam 1 30 (%)
Total 100 (%)
ECTS / Working Load Table
Quantity Duration Total Work Load
Course Week Number and Time 14 3 42
Out-of-Class Study Time (Pre-study, Library, Reinforcement) 14 4 56
Midterms 1 10 10
Quiz 0 0 0
Homework 0 0 0
Practice 0 0 0
Laboratory 10 1 10
Project 1 5 5
Workshop 0 0 0
Presentation/Seminar Preparation 0 0 0
Fieldwork 0 0 0
Final Exam 1 15 15
Other 0 0 0
Total Work Load: 138
Total Work Load / 30 4,60
Course ECTS Credits: 5
Course - Learning Outcomes Matrix
Relationship Levels
Lowest Low Medium High Highest
1 2 3 4 5
# Learning Outcomes P2 P4 P5 P7
O1 Ability to know the design of programmable logic arrays 4 - - -
O2 Ability to make hardware description language application - 4 - -
O3 Ability to code FPGA at gate level - - 4 -
O4 Ability to code Behavioural FPGA - - 4 -
O5 Ability to make FPGA application - - 4 -
O6 Ability to prepare and present technical documents such as technical reports and presentations - - - 5