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Course Details
KTO KARATAY UNIVERSITY
Mühendislik ve Doğa Bilimleri Fakültesi
Programme of Electrical and Electronics Engineering
Course Details
Course Code Course Name Year Period Semester T+A+L Credit ECTS
05171707 Computer Architecture 4 Autumn 7 3+0+0 5 5
Course Type Elective
Course Cycle Bachelor's (First Cycle) (TQF-HE: Level 6 / QF-EHEA: Level 1 / EQF-LLL: Level 6)
Course Language Turkish
Methods and Techniques -
Mode of Delivery Face to Face
Prerequisites -
Coordinator Prof. Novruz ALLAHVERDİ
Instructor(s) -
Instructor Assistant(s) -
Course Content
Advanced processor structures: CISC/RISC architectures, pipeline structure, array processors, interleaved memory. Floating point computer arithmetic and algorithms. Input-output organization: data transfer methods, interrupts and direct memory access. Memory hierarchy, virtual memory, cache memory, memory management hardware. Multiprocessor architectures: interconnection structure, bus arbitrations, cache coherence
Objectives of the Course
To teach how to choose and design an instruction set. To teach basic techniques of pipelining. To teach I/O subsystem including nested interrupts and DMA To teach hierarchical memory subsystems including disk subsystem, processor caches, virtual memory, memory error correction. To teach multiprocessing and concurrency concepts.
Contribution of the Course to Field Teaching
Basic Vocational Courses
Specialization / Field Courses
Support Courses
Transferable Skills Courses
Humanities, Communication and Management Skills Courses
Weekly Detailed Course Contents
Week Topics
1 Introduction to computer architecture
2 Advanced processor structures: CISC/RISC architectures, pipeline structure, array processors, interleaved memory
3 Advanced processor structures: CISC/RISC architectures, pipeline structure, array processors, interleaved memory
4 Floating point computer arithmetic and algorithms
5 Floating point computer arithmetic and algorithms
6 Input-output organization: data transfer methods, interrupts and direct memory access
7 Input-output organization: data transfer methods, interrupts and direct memory access
8 Interrupts examples
9 Midterm
10 Direct Memory Access, I/O Processors
11 Memory hierarchy, virtual memory, cache memory, memory management hardware
12 Memory hierarchy, virtual memory, cache memory, memory management hardware
13 Multiprocessor architectures: interconnection structure, bus arbitrations, cache coherence
14 Multiprocessor architectures: interconnection structure, bus arbitrations, cache coherence
Textbook or Material
Resources M. Morris Mano, Computer System Architecture, 3/e, Prentice Hall,1993
Evaluation Method and Passing Criteria
In-Term Studies Quantity Percentage
Attendance - -
Laboratory - -
Practice - -
Homework - -
Presentation - -
Projects - -
Quiz - -
Listening - -
Midterms - -
Final Exam - -
Total 0 (%)
ECTS / Working Load Table
Quantity Duration Total Work Load
Course Week Number and Time 0 0 0
Out-of-Class Study Time (Pre-study, Library, Reinforcement) 0 0 0
Midterms 0 0 0
Quiz 0 0 0
Homework 0 0 0
Practice 0 0 0
Laboratory 0 0 0
Project 0 0 0
Workshop 0 0 0
Presentation/Seminar Preparation 0 0 0
Fieldwork 0 0 0
Final Exam 0 0 0
Other 0 0 0
Total Work Load: 0
Total Work Load / 30 0
Course ECTS Credits: 0